1. Field of the Invention
This invention relates to a dynamic semiconductor memory device (DRAM) formed with high integration density.
2. Description of the Related Art
The integration density of a DRAM having one-transistor/one-capacitor memory cells is markedly enhanced with the further development of the fine patterning process. In the DRAM, the magnitude of a signal read out and supplied to the bit line is determined by the ratio C.sub.s /C.sub.B of the capacitance C.sub.s of the capacitor to the capacitance C.sub.B of the bit line and a power source potential V.sub.cc. When the cell area is reduced to form the DRAM with high integration density, the capacitance C.sub.s of the capacitor becomes small and the capacitance C.sub.B of the bit line is increased with an increase in the integration density. Therefore, since the magnitude of a signal to be detected by a sense amplifier is reduced with an increase in the integration density of the DRAM, the reliability of the DRAM is lowered.
In the prior art, in order to obtain a large capacitance of the capacitor with small area, trench capacitors and stacked capacitors have been proposed. However, even if the above capacitors are used, there is a restriction on the increase of the capacitance of the capacitor. In order to reduce the bit line capacitance, a method of dividing the bit line so as to reduce the length of a bit line connected to a sense amplifier is effective. However, if the number of divisions of the bit line becomes large, the number of sense amplifiers is increased accordingly, thereby increasing the chip area. Thus, reduction in the bit line capacitance by the bit line division is limited. The magnitude of a readout signal becomes larger as the power source potential V.sub.cc becomes higher, but since the withstanding voltage and reliability of the elements are lowered with greater miniaturization of the elements, it is required to lower the power source potential V.sub.cc.
For the above reasons, it becomes difficult to increase the magnitude of a signal read out on the bit line and at the same time enhance the integration density of the DRAM.
Further, with an increase in the integration density of the DRAM, a problem of noises appearing on the bit line occurs. One of the bit line noises is caused by the capacitive coupling between the bit lines. That is, since the bit lines are arranged with a small pitch, the bit line noise becomes extremely large. The other noise is caused by the capacitive coupling between the bit line and a word line which is arranged to cross the bit line. The word line and bit line are arranged to cross each other with an inter-level insulation film disposed therebetween and the inter-level insulation film becomes thinner as the integration density becomes higher. This is because the aspect ratio of a contact hole for the bit line must be made as small as possible. Therefore, the amount of noise transmitted from the word line to the bit line is increased with an increase in the integration density of the DRAM.
The high-speed operation of the bit line sense amplifier will be degraded by a reduction in the magnitude of a readout signal and an increase in the noise with an increase in the integration density of the DRAM. In general, the bit line sense amplifier is constructed by a flip-flop. The sensitivity of the bit line sense amplifier is determined by the degree of variation in the threshold voltages of MOS transistors constituting the flip-flop. Therefore, when the bit line sense amplifier constituted by MOS transistors whose threshold voltages are not constant is operated at a high speed, "0" or "1" of a small signal read out on the bit line may be erroneously determined.
As described above, in the conventional DRAM, the magnitude of a signal appearing on the bit line is further reduced and the amount of bit line noise is increased by a reduction in the capacitance of the capacitor, increase in the capacitance of the bit line, lowering in the power source potential and the like caused with an increase in the integration density. Therefore, unless the above problems are solved, it is difficult to further enhance the integration density of the DRAM. Further, in order to correctly operate the bit line sense amplifier irrespective of reduction in the magnitude of a signal read out on the bit line, the high-speed operation of the bit line sense amplifier must be sacrificed.
As the related document of this invention, an article by N. Matsukawa et al., "A BIPOLAR-EPROM (BI-EPROM) STRUCTURE FOR 3.3 V OPERATION AND HIGH SPEED APPLICATION", Technical Digest of IEDM, pp. 313-316, IEEE 1990 is provided.